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Title:          Brusey20 State Machine to VHDL Translator
Version:        2.3
Entered-date:   November 15, 1996
Description:    Brusey20 is used to translate a state diagram into
                synthesizable VHDL.  The state diagram may be entered
                with XFig, a free drawing tool.  The format which
                brusey20 accepts is the PIC format, which may be
                exported by XFig.  Output is at least suitable for
                synthesis using Exemplar's Galileo.  It may also be
                useful for other synthesizers.
Keywords:       VHDL, state, machine, synthesis
Author:         tcmayo@fang.berk.net (Tom Mayo)
Maintained-by:  tcmayo@fang.berk.net (Tom Mayo)
Primary-site:   sunsite.unc.edu /pub/Linux/apps/circuits
Alternate-site: 
Original-site:  fang.berk.net
Platform:       
Copying-policy: GNU Public License, Version 2
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