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Icarus Verilog is a Verilog simulation and synthesis tool.  It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some 
target format.  For batch simulation, the compiler can generate an intermediate
form called vvp assembly.  This intermediate form is executed by the 'vvp' 
command.  For synthesis, the compiler generates netlists in the desired format.

 Name                                          Last modified      Size  
 Parent Directory                                                   -   
 README                                        27-May-2010 00:00  387   
 slack-desc                                    27-May-2010 00:00  781   
 verilog.SlackBuild                            15-Apr-2011 00:00  2.1K  
 verilog.info                                  15-Apr-2011 00:00  319   

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