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ADMS is a code generator for the Verilog-AMS language

ADMS is a code generator that converts electrical compact
device models specified in high-level description language into
ready-to-compile C code for the API of spice simulators. Based on
transformations specified in XML language, ADMS transforms Verilog-AMS
code into other target languages.

 Name                                                          Last modified      Size  
 Parent Directory                                                                   -   
 README                                                        04-Jun-2022 07:55  348   
 adms-2.3.7.tar.gz                                             04-Jun-2022 07:55  803K  
 adms.SlackBuild                                               02-Apr-2022 13:23  3.0K  
 adms.info                                                     04-Jun-2022 07:55  350   
 slack-desc                                                    04-Jun-2022 07:55  891   

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