V8(lMarvell RD-AC5X Board)marvell,rd-ac5xmarvell,ac5xmarvell,ac5"1cpus"1cpu-mapcluster0core0=core1=cpu@0Acpuarm,cortex-a55MQpsci_pcpu@1Acpuarm,cortex-a55MQpsci_pl2-cachecachexppsci arm,psci-0.2Xsmctimerarm,armv8-timer0  pmuarm,cortex-a55-pmu  soc simple-bus"1internal-regs@7f000000"1 simple-busserial@12000snps,dw-apb-uartM  Sokayserial@12100snps,dw-apb-uartM! T disabledserial@12200snps,dw-apb-uartM" U disabledserial@12300snps,dw-apb-uartM# V disabledmdio@22004"1marvell,orion-mdioM ethernet-phy@0Mp i2c@11000marvell,mv78230-i2cM "1core W defaultgpio   okayi2c@11100marvell,mv78230-i2cM "1core X defaultgpio    okaygpio@18100marvell,orion-gpioM@( /?K Wj0KLMNpgpio@18140M@@marvell,orion-gpio(/?K WjOPbus@80500000 simple-bus"1MPmmc@805c0000-marvell,ac5-sdhcimarvell,armada-ap806-sdhciM\ \  coreaxiokaybehind-32bit-controller@7f000000 simple-bus"1ethernet@20000marvell,armada-ac5-netaM@ -sgmiiokay ethernet@24000marvell,armada-ac5-netaM@@ 7sgmii disabledusb@80000marvell,orion-ehciM Cokayusb@a0000marvell,orion-ehciM  Eokayusb-phy peripheralpinctrl@80020100marvell,ac5-pinctrlM p i2c0-pins  mpp26mpp27i2c0pi2c0-gpio-pins  mpp26mpp27gpiopi2c1-pins  mpp20mpp21i2c1p i2c1-gpio-pins  mpp20mpp21i2c1p spi@805a0000marvell,armada-3700-spiMZP"1 Z'okayflash@0jedec,spi-nor.@QM"1partition@0bspi_flash_part0Mparition@1bspi_flash_part1Mpparition@2bspi_flash_part2Mspi@805a8000marvell,armada-3700-spiMZP"1 [' disablednand-controller@805b0000marvell,ac5-nand-controllerM[T"1 Y disabledinterrupt-controller@80600000 arm,gic-v3j M`f pclockscnm-clock fixed-clockh_@pspi-clock fixed-clockh pnand-clock fixed-clockhׄpemmc-clock fixed-clockhׄp aliases)u/soc/internal-regs@7f000000/serial@12000}/soc/spi@805a0000/flash@0'/soc/internal-regs@7f000000/gpio@18100'/soc/internal-regs@7f000000/gpio@181405/soc/behind-32bit-controller@7f000000/ethernet@200005/soc/behind-32bit-controller@7f000000/ethernet@24000memory@0AmemoryM@usb-phyusb-nop-xceivp modelcompatibleinterrupt-parent#address-cells#size-cellscpudevice_typeregenable-methodnext-level-cachephandlecache-levelcache-unifiedinterruptsrangesdma-coherentreg-shiftreg-io-widthclocksstatusclock-namesclock-frequencypinctrl-namespinctrl-0pinctrl-1scl-gpiossda-gpiosngpiosgpio-controller#gpio-cellsgpio-rangesmarvell,pwm-offsetinterrupt-controller#interrupt-cellsdma-rangesbus-widthnon-removablemmc-ddr-1_8vmmc-hs200-1_8vmmc-hs400-1_8vphy-modephy-handlephysphy-namesdr_modemarvell,pinsmarvell,functionnum-csspi-max-frequencyspi-tx-bus-widthspi-rx-bus-widthlabel#clock-cellsserial0spiflash0gpio0gpio1ethernet0ethernet1#phy-cells